This invention relates to the field of integrated electronic circuits of the variety wherein a plurality of different circuit types are received on a semiconductor carrier substrate and interconnected by metal conductors received on the carrier substrate.
Frequently in the design of a complex electronic system, such as a flight control computer or a radar for a modern day aircraft, there is a need to collect a variety of differing types of electronic circuitry into a single system. This need is often combined with the need for circuits that are as small and lightweight as possible and are also free of "pinout" and other conventional circuit interconnection limitations. Frequently, the circuits to be collected into one of these complex systems are of such diversity as being of both the analog and digital signal processing types, functioning with signal levels of differing amplitudes, functioning at significantly different operating speeds or operating frequencies, and in more recent systems, operating via the combination of optically and electrically coded signal types.
Often in such systems, it is therefore common to encounter individual integrated circuit die which are fabricated in accordance with a diversity of different processing technologies including, for example, die materials operating with oppositely charged carrier types, that is, p-type and N-type semiconductor materials, circuits of drastically different active device categorization, MOS and bipolar transistor types, for example, and circuits fabricated according to different design rules, circuits with three micron geometry features, for example, in combination with circuits possessing submicron geometry features.
Clearly, the prospect for combining circuits of this large variety on a single large scale integration wafer by using conventional circuit fabrication techniques are nearly if not totally impossible. Any one of the above cited circuit difference examples would in all reality frustrate even the best of the present day large scale integration circuit design teams in an attempt at single wafer integration.
The well known practice of mounting integrated circuit die in multiply pinned packages which are then soldered or otherwise attached to a printed circuit board has been used as a means to package combinations of diverse circuit die on a common substrate. Circuitry packaged in this manner is severely limited with respect to packaging density due to inductive and capacitive electrical coupling effects--a result of long interconnecting conductors; susceptibility to thermal and physical stressing events; weight penalties and "pinout" limitations.
Workers who have recognized these difficulties have attempted to combine a plurality of different circuit types on a single wafer by extending the concept of an integrated circuit package into the realm of plural diverse circuit die received on a single large wafer. By regarding the wafer as a packaging device and connecting individual die to the package using conventional techniques, these workers arrived at a form of wafer scale integration. A number of problems, including difficulties with the wire bonding used to electrically connect die and wafer, and difficulties in achieving permanent attachment between die and wafer have precluded the achievement of notable success in these efforts. Notwithstanding these difficulties with both the wafer integration and printed circuit approaches, the need for maximum flexibility in combining a variety of circuit types, increases in modern electronic systems, particularly in military and other state of the art systems.
The present invention provides an advancement in the state of this die and wafer combination art, that is the wafer scale integration art, to a level enabling its practical use in even military and other critical circuit applications. By way of incorporating a plurality of improvements in previously attempted die to wafer combinations, the present invention accomplishes these combinations at modest cost and with desirable reliability and manufacturing ease.
The combination of silicon circuit die with a silicon substrate member, notwithstanding the previously encountered practical difficulties, is herein shown to offer desirable real life advantages including minimum size and weight penalties, significant heat conduction away from the die by the silicon or other material of a wafer, ability to control substrate electrical characteristics via substrate doping, substantially identical thermal coefficients of expansion between die and supporting substrate, and the ability to elect employed substrate properties through the selection of optimum Miller index crystal orientation in the substrate.
An arrangement wherein an integrated circuit chip is mounted on a ceramic carrier by embedding or encapsulating the chip in an epoxy resin is shown in the patent of B.M. Hargis, U.S. Pat. No. 3,864,810. The use of solderable connections and several layers of ceramic material, distinguish the present invention from the teachings of the Hargis patent.
Another integrated circuit mounting arrangement wherein the integrated circuit die are enclosed by an epoxy encapsulant is shown in the patent of F.A. Perrino, U.S. Pat. No. 3,868,724. In the Perrino mounting arrangement, sets of leads are formed on a flexible tape carrier with the leads penetrating through holes in the tape and terminating in contacts which are arranged in a pattern corresponding to the contact pattern of the integrated circuit die. A tape carrier distinguishes the present invention from the perrino arrangement.
The patent of Honn et al, U.S. Pat. No. 4,074,342 discloses an integrated circuit chip carrier arrangement in which a carrier and a semiconductor material with similar thermal expansion coefficients are employed. The use of solder technology to interconnect various portions of the Honn et al apparatus distinguishes the present invention from the teachings of Honn et al.
The patent art also indicates that the mounting of integrated circuit die in a receptacle well portion of a semiconductor wafer has been attempted by several workers in the art. Included in these efforts is the work of K. L. Tai which is the subject of U.S. Pat. No. 4,670,770. In the Tai invention, the beveled sides of an isotropically etched receptacle well are mated with similarly beveled sides of the integrated circuit die being mounted using metallic conductor members received on both the receptacle well walls and the die surface. Preferably the Tai conductors are of solder wettable material. The use of conductor elements in a die to wafer retention capacity and the use of solder based materials in the Tai invention are distinguished from the arrangements described in the present invention.
A surface mounting arrangement for integrated circuit die is disclosed in U.S. Pat. No. 4,685,030 of J. Reyes. In the Reyes invention, surface mounting of the integrated circuit die is shown together with thick film interconnection and resistor patterns that are disposed on an insulating substrate. The Reyes invention contemplates the use of low pressure chemical vapor deposition for the conductors together with soldering of interconnecting terminals. The Reyes deposited metal is selected from the group of manganese, chromium, cobalt, nickel, molybdenum, tungsten, and alloys of these metals. The die surface mounting, metallic bonding of die to wafer, use of quartz or alumina wafers, and selected conductor materials are all points of contrast between the instant invention and the Reyes patent.
The patent of R. Percival, U.S. Pat. No. 4,689,657 disclosed an integrated circuit interconnecting arrangement which uses an electrically conducting film containing standardized openings and a prearranged raster configuration. Selected portions of the Percival raster are subsequently removed by a laser, for example, in order to achieve a desired circuit configuration. The Percival invention also employs the laser for exposure of a photo sensitive film used in producing the isolated conductive areas of the conductive film in a photo etching process.
An integrated circuit die mounting arrangement of the inverted die and mesa interface type is shown in the patent of A. N. Patraw, U.S. Pat. No. 4,695,870. In the Patraw invention, a mesa interface member is joined to the face of the integrated circuit die and through an internal conductor carrier member. Although the patraw die mounting arrangement considerably shortens the length of the bonding wires that join the integrated circuit chip with electrical conductors residing on the chip carrier, it is notable that such bonding wires are nevertheless a necessary portion of the circuit arrangement.
The patent of D. F. Sullivan, U.S. Pat. No. 4,756,929 concerns a printed circuit board arrangement for circuit mounting in which the conductors are provided with photopolymer formed U-shaped cross sections. The printed circuit board nature of the Sullivan invention and the conductor arrangement espoused by Sullivan readily distinguish the teachings of the Sullivan patent from the present invention.
As is suggested by these patents and the preceding discussion, the electronic art continues to need a more satisfactory wafer scale integration arrangement, an arrangement which especially achieves the ability to receive integrated circuit die of differing process technology as well as different electrical function in a common and small sized physical package that also provides a flexible interconnection arrangement.